| Parameters | |
|---|---|
| Series | CoolRunner II |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| RoHS Status | ROHS3 Compliant |
| Package / Case | 100-TQFP |
| Mfr | AMD |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 70°C (TA) |
| Supplier Device Package | 100-VQFP (14x14) |
| Number of I/O | 80 |
| Number of Gates | 6000 |
| Programmable Type | In System Programmable |
| Voltage Supply - Internal | 1.7V ~ 1.9V |
| Number of Logic Elements/Blocks | 16 |
| Delay Time tpd(1) Max | 5.7 ns |
| Number of Macrocells | 256 |
| Package | Tray |
| Product Status | Active |
| Conevo-Key Programmable | Not Verified |
| Base Product Number | XC2C256 |
| REACH Status | REACH Unaffected |
| Standard Package | 90 |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
XC2C256-6VQG100C CPLD
The XC2C256-6VQG100C is a high-performance, low-power Complex Programmable Logic Device (CPLD) from Xilinx (AMD), belonging to the CoolRunner-II family with 256 macrocells, approximately 6,000 system gates, and 80 user I/Os housed in a compact 100-pin VQFP (14x14mm) surface-mount package. Built on 0.18μm CMOS technology, it operates at a core voltage of 1.7V to 1.9V (optimized for 1.8V) and features non-volatile, instant-on configuration with in-system programmability (ISP), ensuring reliable logic retention without external memory and enabling easy field upgrades. This device delivers high-speed performance with a 5.7ns maximum propagation delay, supports up to 256MHz operation, and integrates advanced power-saving features like DataGATE and CoolCLOCK, making it ideal for cost-sensitive, low-power industrial, automotive, and consumer electronics applications.
It provides 256 macrocells organized into 16 logic array blocks (LABs), delivering around 6,000 equivalent system gates and 80 user-configurable I/Os for flexible logic implementation. Operating from 1.7V to 1.9V core supply, it achieves ultra-low power consumption with a typical standby current of 16μA and a static power of 28.8μW, significantly reducing energy use compared to traditional CPLDs. The device offers high-speed performance with a 5.7ns pin-to-pin delay, supports system frequencies up to 256MHz, and features in-system programmability (ISP) for easy configuration and reconfiguration.
Alternative CPLD Models
● Lattice Semiconductor LC256-7VQ100C: 256-macrocell CPLD in 100-VQFP, 1.8V core, 7ns delay, and commercial temperature range as a pin-compatible, cost-effective alternative.
● Microchip ATF2500C-100VQFP: 256-macrocell CPLD with 1.8V operation, 6ns propagation delay, and 80 I/Os for industrial and automotive logic applications.
● Intel (Altera) EPM256T100C5: 256-macrocell MAX II CPLD in 100-VQFP, 1.8V core, 5.5ns delay, and in-system programmability for high-speed designs.