| Parameters | |
|---|---|
| Series | - |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| RoHS Status | RoHS non-compliant |
| Package / Case | 20-LCC (J-Lead) |
| Mfr | AMD |
| Mounting Type | Surface Mount |
| Operating Temperature | -40°C ~ 85°C |
| Supplier Device Package | 20-PLCC (9x9) |
| Memory Size | 2Mb |
| Voltage - Supply | 3V ~ 3.6V |
| Programmable Type | OTP |
| Package | Tube |
| Product Status | Obsolete |
| Conevo-Key Programmable | Not Verified |
| Base Product Number | XC17V02 |
| REACH Status | REACH Unaffected |
| Standard Package | 46 |
| ECCN | EAR99 |
| HTSUS | 8542.32.0071 |
XC17V02PC20I OTP configuration PROM
The XC17V02PC20I is a 2-Mbit OTP configuration PROM manufactured by AMD Xilinx (originally Xilinx Inc.), belonging to the XC17V00 family of low-cost, high-density serial configuration memories purpose-built for storing Xilinx FPGA bitstreams. Housed in a 20-pin PLCC surface-mount package and shipped in tube packaging, this device operates from a 3 V to 3.6 V supply (3.3 V nominal) and is specified for the industrial temperature range of -40 °C to +85 °C. As an OTP serial PROM with 2 Mb of memory organized as 2M x 1, the XC17V02PC20I is engineered to configure Xilinx FPGAs via the FPGA serial configuration mode interface, where the FPGA in Master Serial mode generates a configuration clock that drives the PROM and reads bitstream data on the DATA output pin.
Given its role as a dedicated FPGA configuration PROM, the XC17V02PC20I is predominantly deployed in legacy and long-lifecycle electronic systems where Xilinx Virtex-series FPGAs (such as XCV200E through XCV300E) require non-volatile, instant-on configuration at power-up. In industrial automation and control equipment, it serves as the configuration source for FPGAs implementing PLC logic, motor control algorithms, and real-time processing, benefiting from the device's industrial temperature rating and 20-year data retention. Telecommunications infrastructure, including routers, switches, and base-station equipment, relies on the XC17V02PC20I to store FPGA firmware and configuration data that must remain intact across power cycles without external boot assistance. Test-and-measurement instruments, military and aerospace programmable logic modules, and medical imaging systems leverage its cascadable architecture to accommodate larger or multi-image bitstreams.
Alternative FPGA configuration PROM Models
● XC18V02PC20: The Xilinx/AMD in-system reprogrammable (ISP) successor to the XC17V02PC20I in the identical 20-PLCC package and pinout, offering the same 2 Mb density with JTAG readiness and boundary-scan for field-updatable FPGA configuration, representing the recommended migration path for new designs.
● XC17V01PC20I: A lower-density (1 Mb) XC17V00-family OTP configuration PROM in the same 20-PLCC industrial-grade package, suitable for smaller FPGAs or cost-sensitive applications that do not need the full 2 Mb capacity.
● XC17V04PC44I: A higher-density 4 Mb XC17V00 OTP PROM in the 44-PLCC industrial package, serving as a pin-compatible upgrade for configurations requiring greater bitstream storage within the same OTP architecture.