XC9572-10TQ100C
| Parameters | |
|---|---|
| Series | XC9500 |
| Moisture Sensitivity Level (MSL) | 3 (168 Hours) |
| RoHS Status | RoHS non-compliant |
| Package / Case | 100-LQFP |
| Mfr | AMD |
| Mounting Type | Surface Mount |
| Operating Temperature | 0°C ~ 70°C (TA) |
| Supplier Device Package | 100-TQFP (14x14) |
| Number of I/O | 72 |
| Number of Gates | 1600 |
| Programmable Type | In System Programmable (min 10K program/erase cycles) |
| Voltage Supply - Internal | 4.75V ~ 5.25V |
| Number of Logic Elements/Blocks | 4 |
| Delay Time tpd(1) Max | 10 ns |
| Number of Macrocells | 72 |
| Package | Tray |
| Product Status | Obsolete |
| Conevo-Key Programmable | Not Verified |
| Base Product Number | XC9572 |
| REACH Status | REACH Unaffected |
| Standard Package | 90 |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
XC9572-10TQ100C CPLD XC9500 CPLD
The XC9572-10TQ100C is a high-performance Complex Programmable Logic Device (CPLD) from Xilinx's XC9500 family, featuring a 5V core voltage and advanced in-system programmability (ISP) via the IEEE 1149.1 JTAG interface. This device integrates 72 macrocells (equivalent to approximately 1600 usable gates) organized into four 36V18 Function Blocks, each connected by the FastCONNECT II switch matrix for superior pin-locking and routability. It delivers a maximum pin-to-pin propagation delay of 10 ns, supporting system clock frequencies up to 111.1 MHz. Housed in a 100-pin Thin Quad Flat Pack (TQFP) measuring 14x14mm, it provides 72 user I/O pins that are 5V tolerant, allowing direct interfacing with 5V, 3.3V, and 2.5V systems without external buffers. Key features include a minimum endurance of 10,000 program/erase cycles, full commercial temperature range operation (0°C to +70°C), and robust Schmitt trigger inputs for improved noise immunity.
Alternative CPLD Models
1. ATF1502AS-10JC44 (Microchip): A 5V CPLD with 32 macrocells in a 44-pin PLCC package, offering lower density but similar 5V ISP capabilities for simpler designs.
2. EPM7128SLC84-10 (Intel/Altera): A MAX 7000S series CPLD with 128 macrocells in an 84-pin PLCC, providing higher logic capacity and JTAG ISP in a different package footprint.
3. LC4032V-10TN48C (Lattice Semiconductor): A 3.3V ispMACH 4000V CPLD with 32 macrocells in a 48-pin TQFP, suitable for low-power, space-constrained designs requiring voltage migration.
