PGA4311U/1KG4

Features for the PCM5121

Register-Selectable Audio-Processing Functions up to 48-kHz fS

Dynamic Range Control (DRC)

Equalization (EQ)

Filtering

DAC Functionality to 384-kHz fS

Market-Leading Low Out-of-Band Noise

Selectable Digital-Filter Latency and Performance

No DC-Blocking Capacitors Required

Integrated Negative Charge Pump

Intelligent Muting System; Soft Up or Down Ramp and Analog Mute for 120-dB Mute SNR

Integrated High-Performance Audio PLL With BCK Reference to Generate SCK Internally

Accepts 16-, 20-, 24-, and 32-Bit Audio Data

PCM Data Formats: I2S, Left-Justified, Right-Justified, TDM / DSP

SPI or I2C Control

Software or Hardware Configuration

Automatic Power-Save Mode When LRCK and BCK are Deactivated

1.8-V or 3.3-V Failsafe LVCMOS Digital Inputs

Single Supply Operation:

3.3-V Analog, 1.8-V or 3.3-V Digital

Integrated Power-On Reset

Small28-Pin Package

Description for the PCM5121

The PCM512x devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM512x uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Members of the PCM512x family integrate preset audio processing functions with programmable coefficients, allowing developers to change the characteristics of the interpolation filter, speaker EQ, dynamic range controls, and average volume control in their products.

The PCM512x provides 2.1-VRMS ground-centered outputs, allowing designers to eliminate DC-blocking capacitors on the output, as well as external muting circuits traditionally associated with single supply line drivers.

The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ. By supporting loads down to 1 kΩ, the PCM512x can essentially drive up to 10 products in parallel (LCD TV, DVDR, AV receivers, and so forth).

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection, along with reducing system EMI.