STMicroelectronics(ST), a global leader in the semiconductor industry, has been committed to innovating chip packaging and testing manufacturing technologies. Recently, the company announced the construction of a pilot production line in Tours, France, to develop next-generation Panel-Level Packaging (PLP) technology. This project not only reflects ST's strategic layout in the field of advanced packaging technology but also signifies its determination to improve manufacturing efficiency, reduce costs, and expand application areas.

PLP technology is an advanced automated chip packaging and testing manufacturing technology that significantly increases production throughput by using larger rectangular substrates instead of traditional round wafers as chip carriers. It is more suitable for large-scale, high-efficiency mass production. Additionally, PLP technology helps further reduce chip size, enhance performance and cost-effectiveness, and is a key driver in creating the next generation of smaller, more powerful, and more cost-effective electronic devices.

Updates on the Pilot Production Line Construction

The construction of ST's PLP pilot production line in Tours is progressing smoothly and is expected to commence operations in the third quarter of 2026. The project has received an investment of $60 million and has been supported by the local R&D ecosystem. The construction of this pilot production line will help ST further develop and optimize PLP technology for applications in a wider range of products, such as automotive, industrial, and consumer electronics.

Technical Advantages and R&D Network

ST's PLP technology focuses on Direct Copper Interconnect (DCI), which replaces the traditional wire connections of chips with packaging support. This reduces power loss, enhances heat dissipation, and is more conducive to miniaturization, resulting in better overall power density. In addition, PLP technology offers the following advantages:

● Increased production efficiency: By using large square panels, PLP technology can process more ICs at the same time, thereby increasing production efficiency.

● Cost reduction: PLP technology reduces production costs by reducing production steps and increasing automation levels.

● Improved product performance: PLP technology can achieve smaller chip sizes and higher performance, meeting the market's demand for miniaturized and high-performance electronic devices.

The construction of ST's PLP pilot production line relies on its global R&D network, including the first-generation PLP production line in Malaysia. In addition, the Tours PLP pilot production line will also generate synergies with the local R&D ecosystem, including the CERTEM R&D center. The construction of this global cooperation and R&D network not only helps ST maintain its leading position in the field of PLP technology but also provides strong support for the development of the entire semiconductor industry.

Future Outlook

ST's PLP pilot production line in Tours is expected to start operations in the third quarter of 2026. The successful implementation of this project will bring new breakthroughs for ST in the field of advanced packaging technology and further consolidate its competitiveness in the global semiconductor market. With the continuous development and application of PLP technology, ST is expected to achieve wider applications in multiple fields such as automotive, industrial, and consumer electronics, driving the entire industry towards more efficient, environmentally friendly, and intelligent development.

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